Optimization of phase-locked loop performance in data recovery systems

Optimized design conditions are presented for a phase-locked loop (PLL) used as a functional block in data recovery systems with the primary function of timing recovery. A mathematical model is presented which takes into account the nonlinear and discrete-time nature of the PLL when used in data recovery applications. Performance attributes for these systems such as acquisition, tracking, and noise are considered. A systematic design procedure is presented which permits quantitative trade-offs among these performance attributes. The validation of the mathematical model and the systematic design procedure on a practical circuit implementation in CMOS technology is described