Analysis of leakage feedback technique

Leakage power consumption has become serious concern for circuit designers. It is expected that leakage power will dominate the total power dissipation in future VLSI circuits. We here propose a new design named “NMOS leakage feedback” which reduces leakage current while saving exact logic state. The circuit technique includes addition of NMOS helper transistors to both pull-up and pull-down paths in order to reduce leakage current without affecting the other parameters of the circuit. Based on simulation with inverter chain using 32nm Berkeley predictive technology model, NMOS leakage feedback approach achieves less area, power and delay over leakage feedback approaches with proper W/L ratio.