DocumentCode :
1140327
Title :
Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction
Author :
Rijnders, L. ; Six, Paul ; De Man, Hugo J.
Author_Institution :
IMEC, Heverlee, Belgium
Volume :
23
Issue :
3
fYear :
1988
fDate :
6/1/1988 12:00:00 AM
Firstpage :
714
Lastpage :
721
Abstract :
A method to design cell libraries for macrocell layouts, which are constructed as an array of cells, is discussed. It is based on symbolic layout and a hierarchical compaction algorithm. This algorithm provides automatic terminal fitting and compacts cells in such a way that translated and mirrored cells are kept identical. The cells can be changed with a set of parameters by a macrocell generator. The compaction technique then guarantees that no design-rule errors occur for any combination of the parameter values. The method also allows easy adaptability to circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established its cells can be used over and over again with different personality matrices for fast generation of correct layout.<>
Keywords :
VLSI; cellular arrays; circuit layout CAD; digital integrated circuits; adaptability to circuit techniques; automatic terminal fitting; compacts cells; constrained cells; design-rule errors; fast generation of correct layout; hierarchical compaction; layout rules; macrocell generator; macrocell layouts; mirrored cells; process-tolerant cell library; regular structures; symbolic layout; translated cells; Application software; Circuits; Compaction; Design methodology; Libraries; Macrocell networks; Process design; Silicon; Very large scale integration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.310
Filename :
310
Link To Document :
بازگشت