DocumentCode :
114043
Title :
Design and implementation of a dynamic weight arbiter for networks-on-chip
Author :
Zhisheng Xu ; Su Zhang ; Wei Ni ; Yanhui Yang ; Jichun Bu
Author_Institution :
Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China
fYear :
2014
fDate :
26-28 April 2014
Firstpage :
354
Lastpage :
357
Abstract :
As there are unbalanced communications between each computing core in multi-core system, a dynamic weight arbiter for networks-on-chip is designed and implemented in this paper. This arbiter uses a simple method to realize static arbitration mechanism based on Lottery algorithm, and on this basis, according to the congestion situation detected in all directions, it uses turn weights approach to dynamically adjust the weights in each direction. This paper has designed three experiments featuring simulating unbalanced communication between multi cores which indicates that dynamic arbitration mechanism based on routing node of dynamic weight arbiter can effectively improve performance of networks-on-chip in case of unbalanced communication between multi cores.
Keywords :
asynchronous circuits; logic design; multiprocessing systems; network-on-chip; Lottery algorithm; dynamic weight arbiter; multicore system; network-on-chip; routing node; static arbitration mechanism; unbalanced communications; Algorithm design and analysis; Computer architecture; Decoding; Dynamic scheduling; Heuristic algorithms; System-on-chip; Very large scale integration; dynamic weight arbiter; lottery algorithm; networks-on-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Science and Technology (ICIST), 2014 4th IEEE International Conference on
Conference_Location :
Shenzhen
Type :
conf
DOI :
10.1109/ICIST.2014.6920401
Filename :
6920401
Link To Document :
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