Title :
Refinement of Unified Random Access Memory
Author :
Ryu, Seong-Wan ; Han, Jin-Woo ; Kim, Chung-Jin ; Choi, Sung-Jin ; Kim, Sungho ; Kim, Jin-Soo ; Kim, Kwang Hee ; Oh, Jae-Sub ; Song, Meyong-Ho ; Lee, Gi-Sung ; Park, Yun Chang ; Kim, Jeoung Woo ; Choi, Yang-Kyu
Author_Institution :
Div. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon
fDate :
4/1/2009 12:00:00 AM
Abstract :
This paper investigates how gate height (Hg), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower Hg yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower Hg shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM.
Keywords :
DRAM chips; MOSFET; impact ionisation; silicon-on-insulator; FinFET SONOS device; charge storage; gate height; impact ionization; nonvolatile memory; one-transistor DRAM; partially depleted silicon-on-insulator region; retention characteristics; unified random access memory; Controllability; FinFETs; Helium; Impact ionization; Nonvolatile memory; Random access memory; SONOS devices; Scalability; Silicon on insulator technology; System-on-a-chip; FinFET; SONOS; gate height; nonvolatile memory; one-transistor DRAM (1T-DRAM); partially depleted silicon-on-insulator (PDSOI); unified random access memory (URAM);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2008.2012292
