• DocumentCode
    1140996
  • Title

    Ternary Rate-Multipliers

  • Author

    Mouftah, H.T. ; Smith, K.C. ; Vranesic, Z.G.

  • Author_Institution
    Department of Electrical Engineering, Queen´´s University
  • Issue
    10
  • fYear
    1980
  • Firstpage
    929
  • Lastpage
    931
  • Abstract
    This correspondence describes an application of COS/MOS integrated circuits in the design of ternary rate-multipliers. The logical implementation of two types of ternary rate-multiplier is described. The first type produces an unevenly spaced output pulse train, while in the second one the output pulses are uniformly spaced. Advantages and disadvantages of the two types are presented.
  • Keywords
    Integrated circuits; rate-multipliers; three-valued logic; Clocks; Costs; Counting circuits; Frequency; Inverters; Logic circuits; Logic design; Logic devices; MOS integrated circuits; Multivalued logic; Integrated circuits; rate-multipliers; three-valued logic;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1980.1675477
  • Filename
    1675477
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1140996