Title :
Composite Parallel Counters
Author_Institution :
Istituto di Elettrotecnica ed Elettronica Politecnico di Milano
Abstract :
A graphical representation is presented for parallel counters, i.e., multiple input combinatorial modules that count the number of inputs being in a given state (normally logic ONE).
Keywords :
Associative processors; carry-shower counters; digital counters; multiple input adders; parallel counter networks; parallel counters; parallel multipliers; response counters; Adders; Analog-digital conversion; Associative memory; Correlators; Counting circuits; Delay; Digital arithmetic; Logic circuits; Network synthesis; Read only memory; Associative processors; carry-shower counters; digital counters; multiple input adders; parallel counter networks; parallel counters; parallel multipliers; response counters;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1980.1675481
