DocumentCode :
1141264
Title :
Designing computer architecture research workloads
Author :
Eeckhout, Lieven ; Vandierendonck, Hans ; Bosschere, KoenDe
Author_Institution :
Ghent Univ., Belgium
Volume :
36
Issue :
2
fYear :
2003
fDate :
2/1/2003 12:00:00 AM
Firstpage :
65
Lastpage :
71
Abstract :
Although architectural simulators model microarchitectures at a high abstraction level, the increasing complexity of both the microarchitectures themselves and the applications that run on them make simulator use extremely time-consuming. Simulators must execute huge numbers of instructions to create a workload representative of real applications, creating an unreasonably long simulation time and stretching the time to market. Using reduced input sets instead of reference input sets helps to solve this problem. The authors have developed a methodology that reliably quantifies program behavior similarity to verify if reduced input sets result in program behavior similar to the reference inputs.
Keywords :
computer architecture; microprocessor chips; performance evaluation; principal component analysis; virtual machines; MinneSPEC; architectural simulators; computer architecture research workloads; microarchitectures; microprocessor design; principal component analysis; program behavior; reduced input sets; reference input sets; time to market; Computational modeling; Computer architecture; Costs; Data analysis; Hardware; Microarchitecture; Microprocessors; Performance analysis; Thumb; Time to market;
fLanguage :
English
Journal_Title :
Computer
Publisher :
ieee
ISSN :
0018-9162
Type :
jour
DOI :
10.1109/MC.2003.1178050
Filename :
1178050
Link To Document :
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