New building block: multiplication-mode current conveyor

Author

Hwang, Y.-S. ; Liu, Wen-Hao ; Tu, S.-H. ; Chen, Jian-Jia

Author_Institution

Dept. of Electron. Eng., Nat. Taipei Univ. of Technol., Taipei

Volume

3

Issue

1

fYear

2009

fDate

2/1/2009 12:00:00 AM

Firstpage

41

Lastpage

48

Abstract

A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mum CMOS 2P4M processes with power supply plusmn 1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is plusmn 200 mV, the loading range is from 1 to 10 kOmega, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85 , the power consumption is 1.08 mW and the chip area without pads is 0.48 times 0.36 mm². The new square summer and analogue divider applications employing MMCCs are also presented.

Keywords

CMOS analogue integrated circuits; SPICE; analogue multipliers; current conveyors; harmonic distortion; low-power electronics; DVCC; HSPICE post-layout simulation; MMCC; THD; TSMC CMOS 2P4M processes; analogue divider; differential voltage current conveyor; folded Gilbert cell; four-quadrant analogue multiplier design; multiplication-mode current conveyor; power 1.08 mW; power consumption; power supply; resistance 1 kohm to 10 kohm; size 0.35 mum; square summer; total harmonic distortion; voltage -1.65 V to 1.65 V; voltage -200 mV to 200 mV;

fLanguage

English

Journal_Title

Circuits, Devices & Systems, IET

Publisher

iet

ISSN

1751-858X

Type

jour

DOI

10.1049/iet-cds:20080156

Filename

4773285