Effects of hot carrier induced interface state generation in submicron LDD MOSFET´s

Author

Wang, Tahui ; Huang, Chimoon ; Chou, P.C. ; Chung, Steve S S ; Chang, Tse-En

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

41

Issue

9

fYear

1994

fDate

9/1/1994 12:00:00 AM

Firstpage

1618

Lastpage

1622

Abstract

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states

Keywords

carrier mobility; hot carriers; insulated gate field effect transistors; interface electron states; semiconductor device models; 0.6 micron; DC voltage stress; Si:H; conduction charge; degradation; drain current; hot carriers; interface state generation model; interface traps; mobility; silicon-hydrogen bond breaking; submicron LDD MOSFETs; substrate current; two-dimensional numerical simulation; Bonding; Current measurement; DC generators; Degradation; Hot carriers; Interface states; MOSFET circuits; Numerical simulation; Stress; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.310115

Filename

310115