Floating-point processors join forces in parallel processing architectures

Author

Simar, Ray, Jr. ; Koeppen, P. ; Leach, Jeraid ; Marshall, Steve ; Francis, Dave ; Mekras, Greg ; Rosenstrauch, Jeffrey ; Anderson, Scott

Author_Institution

Texas Instruments, Inc., Stafford, TX, USA

Volume

12

Issue

4

fYear

1992

Firstpage

60

Lastpage

69

Abstract

The hardware architecture and software capabilities of the TMS320C40 floating-point digital signal processor are described. The C40 operates at 275 million operations per second (MOPS) and transfers data at a rate of 320 Mbytes/s with a 40-ns cycle time. A key architectural feature of the C40 for parallel computing is the six parallel bidirectional communication ports that permit direct connection and communication between processors in a parallel system. Examples illustrating the use of the C40 in a parallel processing environment are discussed.<>

Keywords

microprocessor chips; parallel architectures; 275 MFLOPS; 320 MByte/s; 320 Mbytes/s; 40 ns; 40-ns cycle time; 50 MFLOPS; C40; TMS320C40; floating-point digital signal processor; hardware architecture; parallel bidirectional communication ports; parallel processing architectures; software capabilities; Application software; Computer architecture; Concurrent computing; Digital signal processing chips; Hardware; Microprocessors; Parallel architectures; Parallel processing; Read only memory; Read-write memory;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.149737

Filename

149737