Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design

This paper provides a quantitative understanding of the relations among supply-voltage scaling, sustainable cycle time, pipeline depth, instruction-level parallelism, and power dissipation. Starting from simple well-established formulas, the analysis show that there is an optimal sizing of the target supply voltage and pipeline stage complexity to minimize power under a performance constraint. The verification of the model on five real processors is reported and discussed, and the application to an ideal microprocessor design or redesign is illustrated.