DocumentCode :
1141707
Title :
Circular BIST with state skipping
Author :
Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume :
10
Issue :
5
fYear :
2002
Firstpage :
668
Lastpage :
672
Abstract :
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.
Keywords :
VLSI; automatic test pattern generation; built-in self test; design for testability; integrated circuit testing; limit cycles; logic testing; DFT; chain interconnect; circular BIST; circular built-in self-test; control complexity; design for testability; hardware overhead; high fault coverage; limit cycles; observation point insertion; pseudorandom pattern generation; random-pattern-resistant faults; scan chains; state skipping logic; test patterns; test per clock scheme; Built-in self-test; Circuit faults; Circuit testing; Clocks; Flip-flops; Limit-cycles; Logic testing; Pattern analysis; Registers; Test pattern generators;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2002.801564
Filename :
1178089
Link To Document :
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