DocumentCode
1141966
Title
A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination
Author
Martínez, Alejandro ; García, Pedro J. ; Alfaro, Francisco J. ; Sánchez, José L. ; Flich, José ; Quiles, Francisco J. ; Duato, José
Author_Institution
Intel Barcelona Res. Center, Univ. Politec. de Catalunya, Barcelona
Volume
20
Issue
1
fYear
2009
Firstpage
13
Lastpage
24
Abstract
Both QoS support and congestion management techniques become essential to achieve good network performance in current high-speed interconnection networks. The most effective techniques traditionally considered for both issues, however, require too many resources for being implemented. In this paper we propose a new cost-effective switch architecture able to face the challenges of congestion management and, at the same time, to provide QoS. The efficiency of our proposal is based on using the resources (queues) used by RECN (an efficient Head-Of-Line blocking elimination technique) also for QoS support, without increasing queue requirements. Provided results show that the new switch architecture is able to guarantee QoS levels without any degradation due to congestion situations.
Keywords
quality of service; telecommunication congestion control; telecommunication network management; telecommunication switching; HOL blocking elimination; QoS provision; congestion management; high-speed interconnection networks; network performance; switch architecture; Interconnection architectures; Parallel Architectures;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/TPDS.2008.62
Filename
4497190
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