Title :
Parallel Compressors
Author :
Gajski, Daniel D.
Author_Institution :
Department of Computer Science, University of Illinois
fDate :
5/1/1980 12:00:00 AM
Abstract :
A subclass of generalized parallel counters, called parallel compressors, is introduced in this correspondence. Under present-day packaging technology, parallel compressors with their higher compression ratio and fewer input/output pins are more efficient in multiple operand addition and multiplication than parallel counters. Cost and time bounds are obtained for schemes using parallel compressors for reduction of N summands to m summands. Furthermore, a method for synthesizing large parallel counters using only one type of parallel compressor is given.
Keywords :
Associative processors; carry-shower counters; content- addressable memory; elementary logic functions; fast multipliers; high-speed arithmetic; multiple-operand addition; parallel counters; Adders; Arithmetic; Compressors; Costs; Counting circuits; Hardware; Image coding; Logic functions; Packaging; Pins; Associative processors; carry-shower counters; content- addressable memory; elementary logic functions; fast multipliers; high-speed arithmetic; multiple-operand addition; parallel counters;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1980.1675589
