Title :
A Mesh-Structured Scalable IPsec Processor
Author :
Wang, Mao-Yin ; Wu, Cheng-Wen
Author_Institution :
Lab. for Reliable Comput., Nat. Tsing HuaUniversity, Hsinchu, Taiwan
fDate :
5/1/2010 12:00:00 AM
Abstract :
IP security (IPsec) protocols are widely used to protect sensitive data over the Internet. For equipment linked by high-bandwidth optical fibers, the throughput requirement usually results in the adoption of high-performance network security processors. In this paper, we propose a parallel mesh-structured IPsec (MIPsec) processor, which executes the IPsec protocols for Internet security gateway applications. We have developed several area-efficient cryptographic IPs embedded in MIPsec to lower silicon cost. Thanks to structural regularity, the simple deterministic programming of MIPsec guarantees high utilization of the hardware. Also, both handshake and contention issues are solved in the scheme, such that performance can be scaled up. Specifically, the 6.23-million-gate MIPsec achieves 10-Gb/s wire speed for each routing direction. The proposed MIPsec is suitable for transport mode or other crypto mix as well.
Keywords :
IP networks; Internet; computer network security; cryptographic protocols; microprocessor chips; parallel architectures; IP security protocol; Internet security gateway application; area efficient cryptographic IP; contention issues; handshake issues; high bandwidth optical fiber; high performance network security processor; mesh structured scalable IPsec processor; parallel architecture; Advanced Encryption Standard (AES); IP security (IPsec); cryptography; hardware design; hash algorithm; network security; parallel architecture;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2016102
