DocumentCode
1142957
Title
Development of Ultrabroadband (DC–50 GHz) Wafer-Scale Packaging Method for Low-Profile Bump Flip-Chip Technology
Author
Cho, Young Seek ; Franklin-Drayton, Rhonda
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Volume
32
Issue
4
fYear
2009
Firstpage
788
Lastpage
796
Abstract
A locally matched flip-chip (LMFC) interconnect that uses a capacitive compensation technique to minimize impedance mismatch in coplanar waveguide lines is described. With an optimum percentage change in capacitance of 55plusmn5%, we observe return loss below 25 dB over 90% of a 50 GHz bandwidth. When compared to a conventional flip-chip method, the minimum performance improvement in return loss is 10 dB and the insertion loss is smooth up to 30 GHz. The LMFC interconnect consists of two micromachined features: 1) an air cavity underneath the chip and 2) local trenches in the transition region of the flip-chip interconnect interface. A comparison of different LMFC interconnect designs to the conventional flip-chip approach is made, and design rules to obtain local trench dimensions are discussed.
Keywords
coplanar waveguide components; flip-chip devices; integrated circuit interconnections; micromechanical devices; wafer level packaging; air cavity; bandwidth 50 GHz; capacitive compensation technique; coplanar waveguide lines; impedance mismatch; local trenches; locally matched flip-chip interconnect; low-profile bump flip-chip technology; micromachined features; ultrabroadband wafer-scale packaging method; Coplanar waveguides; flip-chip devices; gold alloys; interconnected circuits; interconnections; micromachining; tin alloys;
fLanguage
English
Journal_Title
Advanced Packaging, IEEE Transactions on
Publisher
ieee
ISSN
1521-3323
Type
jour
DOI
10.1109/TADVP.2009.2019846
Filename
5169972
Link To Document