Hierarchical Finite-Element Reduction-Recovery Method for Large-Scale Transient Analysis of High-Speed Integrated Circuits

This paper proposes a hierarchical finite-element reduction-recovery method for large-scale transient analysis of high-speed integrated circuits. This method rigorously reduces the matrix of a multilayer system of O(N) to that of a single-cell system of O(1) regardless of the original problem size. More important, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. In addition, the reduction preserves the sparsity of the original system matrix. As a result, the matrix factorization cost is reduced to O(1) by the proposed method. The CPU cost at each time step scales linearly with the number of unknowns. The method is applicable to any Manhattan-type integrated circuit embedded in layered dielectric media. Numerical and experimental results demonstrate the performance of the proposed method.