Title :
A Testable Design of Iterative Logic Arrays
Author :
Parthasarathy, R. ; Reddy, Sudhakar M.
Author_Institution :
Department of Electrical and Computer Engineering, University of Iowa
Abstract :
Testable design of unilateral iterative logic arrays (ILA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-step C-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number (≤4) of columns and a row so that a faulty cell can be located by a test of length proportional to log2p, where p is the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell.
Keywords :
C-testability; fault detection; fault diagnosis; flow table augmentation; iterative logic arrays; one-step C-testability; one-step testability; Circuit faults; Circuit testing; Electrical fault detection; Fabrication; Fault detection; Fault diagnosis; Logic arrays; Logic design; Logic testing; Sufficient conditions; C-testability; fault detection; fault diagnosis; flow table augmentation; iterative logic arrays; one-step C-testability; one-step testability;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1981.1675714
