• DocumentCode
    1143384
  • Title

    Design for Autonomous Test

  • Author

    McCluskey, Edward J. ; Nesbat, Saied Bozorgui

  • Author_Institution
    Center for Reliable Computing, Computer Systems Laboratory, Departments of Computer Science and Electrical Engineering, Stanford University
  • Issue
    11
  • fYear
    1981
  • Firstpage
    866
  • Lastpage
    875
  • Abstract
    A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible.
  • Keywords
    Built-in test; CMOS testing; VLSI testing; design for testability; exhaustive testing; partitioning; self-test; signature analysis; stuck- open faults; test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Integrated circuit testing; Military computing; Sequential analysis; System testing; Test pattern generators; Very large scale integration; Built-in test; CMOS testing; VLSI testing; design for testability; exhaustive testing; partitioning; self-test; signature analysis; stuck- open faults; test pattern generation;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1981.1675717
  • Filename
    1675717
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1143384