Two-dimensional spatio-temporal dynamics of analog image processing neural networks

A typical analog image-processing neural network consists of a 2D array of simple processing elements. When it is implemented with CMOS LSI, two dynamics issues naturally arise: (1) parasitic capacitors of MOS transistors induce temporal dynamics. Since a processed image is given as the stable equilibrium point of temporal dynamics, a temporally unstable chip is unusable; and (2) because of the array structure, the node voltage distribution induces spatial dynamics, and the node voltage distribution could behave in a wild manner which is undesirable for image-processing purposes. This paper derives several explicit formulas and relationships for the 2D dynamics, which are useful for the design and analysis of the class of networks of interest