• DocumentCode
    1143997
  • Title

    Dynamic zero-sensitivity scheme for low-power cache memories

  • Author

    Chang, Yen-Jen ; Lai, Feipei

  • Author_Institution
    Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
  • Volume
    25
  • Issue
    4
  • fYear
    2005
  • Firstpage
    20
  • Lastpage
    32
  • Abstract
    A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip´s total power consumption. Because most bit values read from the cache are 0´s, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.
  • Keywords
    SRAM chips; cache storage; low-power electronics; microprocessor chips; power consumption; DZS scheme; SRAM cell; dynamic zero-sensitivity scheme; low-power cache memory; power consumption; Data mining; Degradation; Differential amplifiers; Energy consumption; Microprocessors; Random access memory; Semiconductor device manufacture; Stability; Virtual manufacturing; Voltage; Bitlines; Cache; DZS; Dynamic zero-sensitivity; Power reduction;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2005.64
  • Filename
    1498736
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1143997