• DocumentCode
    1144016
  • Title

    QSNETII: defining high-performance network design

  • Author

    Beecroft, Jon ; Addison, David ; Hewson, David ; McLaren, Moray ; Roweth, Duncan ; Petrini, Fabrizio ; Nieplocha, Jarek

  • Volume
    25
  • Issue
    4
  • fYear
    2005
  • Firstpage
    34
  • Lastpage
    47
  • Abstract
    QSNETII optimizes interprocessor communication in systems built from standard server building blocks. Its short-message processing unit permits fast injection of small messages, providing ultra-low latency and scalability to thousands of nodes. Thus, in a sense, the high-performance network in a cluster computer is the computer because it largely defines achievable performance, widening the range of the applications a cluster can efficiently execute, as well as defining its scalability, fault tolerance, system software, and overall usability.
  • Keywords
    computer architecture; multiprocessing systems; multiprocessor interconnection networks; parallel processing; peripheral interfaces; QSNETII; cluster computer; high-performance network design; interprocessor communication optimization; server building blocks; short-message processing unit; Application software; Communication standards; Computer networks; Delay; Fault tolerant systems; High performance computing; Network servers; Scalability; System software; Usability; Clusters of Workstations; Communication Protocols; Microprocessors and microcomputers; Network connectivity chips; Supercomputers;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2005.75
  • Filename
    1498738