• DocumentCode
    1144308
  • Title

    Implementation and Performance Evaluation of Computer Families

  • Author

    Snow, Edward A. ; Siewiorek, Daniel P.

  • Author_Institution
    Intel Corporation
  • Issue
    6
  • fYear
    1981
  • fDate
    6/1/1981 12:00:00 AM
  • Firstpage
    443
  • Lastpage
    447
  • Abstract
    This correspondence proposes a model using microcycle and memory read pause times to account for variation in performance between members of a computer family. Wben applied to the DEC PDP-11 and IBM S/360-S/370 families, the model explains over 90 percent of the variation. This model is useful for initial family planning, as well as design of individual family members.
  • Keywords
    Computer design; computer families; performance evaluation; regression analysis; Art; Costs; Delay effects; Design methodology; Digital systems; Large scale integration; Mathematical model; Process design; Regression analysis; Snow; Computer design; computer families; performance evaluation; regression analysis;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1981.1675810
  • Filename
    1675810
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1144308