DocumentCode
1144322
Title
Double-Edge-Triggered Flip-Flops
Author
Unger, S.H.
Author_Institution
Department of Computer Science, Columbia University
Issue
6
fYear
1981
fDate
6/1/1981 12:00:00 AM
Firstpage
447
Lastpage
451
Abstract
A conventional positive-edge-triggered flip-flop (FF) senses and responds to the control input or inputs at the time the clock input is changing from 0 to 1. It does not respond at all to changes in the opposite direction. Negative-edge-triggered FF´s behave in a complementary manner. Thus, these FF´s can respond at most once per clock pulse cycle. It is proposed that double-edge-triggered (DET) FF´s, responding to both edges of the clock pulse would have advantages with respect to speed and energy dissipation.
Keywords
Asynchronous; D-flip-flop; JK-flip-flops; clock pulses; decomposition; edge triggering; flip-flops; sequential circuits; Asynchronous; D-flip-flop; JK-flip-flops; clock pulses; decomposition; edge triggering; flip-flops; sequential circuits;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1981.1675811
Filename
1675811
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