Title :
Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations
Author :
Embabi, S.H.K. ; Damodaran, R.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fDate :
9/1/1994 12:00:00 AM
Abstract :
In this paper, we report on delay models for CMOS, BiCMOS, and BiNMOS inverters. A two-step iterative approach has been adopted to account for the slope of the input waveforms. The Alpha-Power Law model equations have been used for the short-channel MOSFET´s. The effects of high collector current on the base transit time and the current gain are also included in the models of the bipolar transistors. The developed delay models are incorporated in a timing simulator to estimate the propagation delay of chains with mixed CMOS/BiCMOS/BiNMOS gates. The estimates of the simulator deviate from those of HSPICE by less than 10%, while it is faster than HSPICE by two orders of magnitudes. Hence, it can be used for identifying critical paths in VLSI systems
Keywords :
BIMOS integrated circuits; BiCMOS integrated circuits; CMOS integrated circuits; VLSI; circuit analysis computing; delays; equivalent circuits; integrated logic circuits; iterative methods; logic gates; semiconductor device models; BiCMOS circuits; BiNMOS circuits; CMOS circuits; VLSI systems; alpha-power law model equations; base transit time; bipolar transistors; critical paths identification; current gain; delay models; high collector current; inverters; mixed CMOS/BiCMOS/BiNMOS gates; propagation delay; short-channel MOSFET; timing simulations; two-step iterative approach; BiCMOS integrated circuits; Bipolar transistors; Delay estimation; Equations; Inverters; Iterative methods; Propagation delay; Semiconductor device modeling; Timing; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
