• DocumentCode
    1144882
  • Title

    Synthesis of Generalized Parallel Counters

  • Author

    Dormido, S. ; Canto, M.A.

  • Author_Institution
    Departamento de Informática y Automática, Universidad Complutense, Ciudad Universitaria
  • Issue
    9
  • fYear
    1981
  • Firstpage
    699
  • Lastpage
    703
  • Abstract
    Synthesis of generalized equal column parallel counters from smaller ones is presented. The notation used for a general counter is (n × N; d), where n is the number of input columns, N is the number of input bits in each column, and d = s · n (s = 2, 3,···) is the number of bits in the output word.
  • Keywords
    Digital counters; FAST multipliers; multiple-input adders; parallel counters; parallel-counter networks; Arithmetic; Compressors; Counting circuits; Packaging; Read only memory; Digital counters; FAST multipliers; multiple-input adders; parallel counters; parallel-counter networks;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1981.1675870
  • Filename
    1675870
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1144882