Title :
Synthesis of Generalized Parallel Counters
Author :
Dormido, S. ; Canto, M.A.
Author_Institution :
Departamento de Informática y Automática, Universidad Complutense, Ciudad Universitaria
Abstract :
Synthesis of generalized equal column parallel counters from smaller ones is presented. The notation used for a general counter is (n × N; d), where n is the number of input columns, N is the number of input bits in each column, and d = s · n (s = 2, 3,···) is the number of bits in the output word.
Keywords :
Digital counters; FAST multipliers; multiple-input adders; parallel counters; parallel-counter networks; Arithmetic; Compressors; Counting circuits; Packaging; Read only memory; Digital counters; FAST multipliers; multiple-input adders; parallel counters; parallel-counter networks;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1981.1675870
