Title :
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer
Author :
Manganaro, Gabriele ; Kwak, Sung-Ung ; Bugeja, Alexander R.
Author_Institution :
Engim Inc., Acton, MA, USA
Abstract :
A dual 10-b/200-MSPS pipelined digital-to-analog converter (DAC) suitable for communication applications is here presented. Prior implementation limitations have been overcome through circuit techniques. A prototype has been designed using a 4-metal-levels 3.3-V 0.5-μm BiCMOS technology and operates on a 3-phase clock synthesized by an on-chip delay-locked loop (DLL). The DAC shows 9.7 effective bits and 70 dB of spurious free dynamic range for a synthesized sine wave of 2 Vpp at 34 MHz and output rate of 200 MSPS. Altogether, the two DACs, their reference, and the DLL occupy an active area of 2.28 mm2 and consume 693 mW at full speed.
Keywords :
BiCMOS analogue integrated circuits; data conversion; delay lock loops; digital-analogue conversion; frequency synthesizers; integrated circuit design; 0.5 micron; 10 bit; 3-phase clock; 34 MHz; 693 mW; BiCMOS analog integrated circuits; BiCMOS technology; DLL-based clock synthesizer; data conversion; delay-locked loop; digital-to-analog converter; integrated circuit design; pipelined D/A converter; Analog integrated circuits; BiCMOS integrated circuits; Circuit synthesis; Clocks; Delay; Digital-analog conversion; Integrated circuit synthesis; Linearity; Synthesizers; Voltage; Analog integrated circuits; BiCMOS analog integrated circuits; data conversion; delay locked loops; digital–analog conversion; integrated circuit design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.835829
