Thermal characterization of electronic devices with boundary condition independent compact models

The accurate prediction of operating temperatures of temperature-sensitive electronic parts at the component-, board-, and system-level is seriously hampered by the tack of reliable, standardized input data. The situation which prevails today is that component manufacturers supply to end users experimental data which characterizes the thermal behavior of packages under a set of standardized and idealized conditions. Such characterizations normally involve the junction-to-case thermal resistance or the junction-to-ambient resistance according to MIL or SEMI standards. There are several practical difficulties associated with such an approach, which will be shortly commented upon. Today, the need for more accurate junction temperature prediction becomes increasingly urgent, and the call for a precise definition of the various thermal resistances is heard by a growing number of researchers. An earlier paper discussed the pros and cons of several methods that describe the thermal behavior of electronic parts. It was concluded that none of these methods is capable of meeting the objectives that are proposed. In this paper, a novel approach is introduced, based on the derivation of a simple resistance network starting from a detailed model, using optimization techniques. The proposed method is applied to two cases:a so-called “validation” chip, functioning as a benchmark for the software that is used to generate the detailed model; and a 208-PQFP component. It is demonstrated that it is possible to create a compact model comprising a simple resistance network, representing the detailed model to a high accuracy, which is independent of the boundary conditions