Title :
A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS
Author :
Van de Beek, Remco C H ; Vaucher, Cicero S. ; Leenaerts, Domine M W ; Klumperink, Eric A M ; Nauta, Bram
Author_Institution :
Univ. of Twente, Enschede, Netherlands
Abstract :
This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.
Keywords :
CMOS digital integrated circuits; MMIC frequency convertors; clocks; multiplying circuits; phase detectors; phase locked loops; phase noise; timing jitter; voltage-controlled oscillators; 0.18 micron; 1.8 V; 100 mW; 2.5 to 10 GHz; CMOS; LC oscillator; PLL locking; RMS jitter; charge pump; clock generation; clock multiplication; clock multiplier unit; frequency multiplication; frequency synthesizer; internal feedback loop; jitter generation; phase detector circuit; phase frequency detector; phase locked loops; phase noise; voltage-controlled oscillator; CMOS process; Clocks; Feedback circuits; Feedback loop; Frequency locked loops; Jitter; Oscillators; Phase detection; Phase frequency detector; Phase locked loops; CMOS; CMU; Charge pump; PFD; PLL; VCO; clock generation; clock multiplication; clock multiplier unit; frequency detector; frequency multiplication; frequency synthesizer; high speed; low jitter; low noise; phase detector; phase frequency detector; phase locked loops; phase noise; voltage-controlled oscillator;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.835833
