Title :
A high-resolution synchronous mirror delay using successive approximation register
Author :
Sung, Kihyuk ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD . Fine locking is achieved by the successive approximation register for the sake of fast locking . Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-μm 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles.
Keywords :
CMOS integrated circuits; clocks; delay circuits; synchronisation; 0.35 micron; 14.85 mW; 170 to 230 MHz; CMOS technology; clock skew; clock synchronization; coarse locking; external clock; fast locking; fine locking; high-resolution synchronous mirror delay; internal clock; successive approximation register; CMOS technology; Circuits; Clocks; Delay; Mirrors; Phase locked loops; Random access memory; Registers; Robustness; Voltage-controlled oscillators; Clock synchronization; successive approximation register; synchronous mirror delay;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.835816
