Title :
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)
Author :
Eslami, Yadollah ; Sheikholeslami, Ali ; Masui, Shoichi ; Endo, Toru ; Kawashima, Shoichiro
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Ont., Canada
Abstract :
This paper presents two circuit implementations for the differential capacitance read scheme (DCRS) in ferroelectric random-access memories (FeRAM). Compared to the conventional read scheme, DCRS achieves a faster read access by activating the sense amplifiers immediately after a wordline is activated. By relying on the capacitance difference instead of the charge difference, DCRS avoids raising the highly capacitive platelines until after the read is complete. We have implemented this scheme in a 0.35-μm CMOS+Ferro test chip that includes an array of 256 × 32 2T-2C cells. The test chip measures an access time of 45 ns at a power supply of 3 V.
Keywords :
CMOS memory circuits; differential amplifiers; ferroelectric capacitors; ferroelectric storage; integrated circuit design; random-access storage; 0.35 micron; 3 V; 45 ns; CMOS Ferro test chip; capacitance difference; charge difference; differential capacitance read scheme; fast read scheme; ferroelectric random-access memories; highly capacitive platelines; memory circuit design; nondriven plateline; nonvolatile memory; read access; sense amplifiers; Capacitance; Circuits; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Power measurement; Random access memory; Semiconductor device measurement; Testing; Time measurement; Differential capacitance; fast read scheme; ferroelectric memory; memory circuit design; nondriven plateline; nonvolatile memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.835813
