DocumentCode
1145319
Title
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
Author
Chung, Wai ; Lo, Timothy ; Sachdev, Manoj
Author_Institution
Electr. & Comput. Eng. Dept., Univ. of Waterloo, Ont., Canada
Volume
10
Issue
6
fYear
2002
Firstpage
913
Lastpage
918
Abstract
This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages.
Keywords
CMOS digital integrated circuits; VLSI; delay estimation; flip-flops; low-power electronics; VLSI; comparative analysis; digital CMOS circuits; flip-flops performance; low-power flip-flops; low-voltage flip-flops; optimal delay; power dissipation; power-delay product; static dual-edge-triggered flip-flops; CMOS technology; Capacitance; Circuits; Clocks; Delay; Energy consumption; Flip-flops; Frequency; Power dissipation; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2002.808429
Filename
1178860
Link To Document