• DocumentCode
    1145331
  • Title

    Functional vector generation for sequential HDL models under an observability-based code coverage metric

  • Author

    Fallah, Farzan ; Ashar, Pranav ; Devadas, Srinivas

  • Author_Institution
    Fujitsu Labs. of America Inc., Sunnyvale, CA, USA
  • Volume
    10
  • Issue
    6
  • fYear
    2002
  • Firstpage
    919
  • Lastpage
    923
  • Abstract
    Design validation and verification is the process of ensuring correctness of a design described at different levels of abstraction during the design process. Design validation is the main bottleneck in improving design turnaround time. Currently, simulation is the primary methodology for validation of the first description of a design. In this paper we integrate directed search methods and observability-based code coverage metric (OCCOM) computation into an algorithm for generating test vectors under OCCOM for sequential HDL models. A prototype system for design validation under OCCOM has been built. The system uses repeated coverage computation to minimize the number of vectors generated. Experimental results using the test vector generation system are presented.
  • Keywords
    VLSI; circuit CAD; formal verification; hardware description languages; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; observability; design turnaround time; design validation; design verification; directed search methods; functional vector generation; observability-based code coverage metric; satisfiability; sequential HDL models; test vector generation system; Circuit testing; Computational modeling; Hardware design languages; Hybrid power systems; Laboratories; Observability; Process design; Search methods; Sequential analysis; System testing;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2002.808438
  • Filename
    1178861