Title :
A novel self-aligned TiN formation by N/sub 2//sup +/ implantation during two-step annealing Ti-salicidation for submicrometer CMOS technology application
Author :
Chen, C.W. ; Fang, Y.K. ; Hsieh, J.C. ; Liang, M.S.
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A new technology of self-aligned TiN/TiSi/sub 2/ formation using N/sub 2//sup +/ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n/sup +//p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi/sub 2/ contact is 1.2 nA/cm/sup 2/ at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500/spl deg/C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi/sub 2/ and Al for submicron CMOS technology applications.<>
Keywords :
CMOS integrated circuits; Rutherford backscattering; VLSI; annealing; integrated circuit technology; ion implantation; metallisation; titanium compounds; -5 V; 30 min; 500 degC; Al spiking; Al-TiN-TiSi/sub 2/; Al/TiN/TiSi/sub 2/ contact; N/sub 2/; N/sub 2//sup +/ implantation; RBS analysis; Si; ULSI; leakage currents; n/sup +//p junction diodes; reverse-bias leakage current; self-aligned TiN/TiSi/sub 2/ formation; submicrometer CMOS technology; two-step annealing Ti-salicidation; Annealing; Area measurement; Artificial intelligence; CMOS process; CMOS technology; Current measurement; Leakage current; Semiconductor diodes; Tin; Ultra large scale integration;
Journal_Title :
Electron Device Letters, IEEE
