Title :
Memory Interference in Synchronous Multiprocessor Systems
Author :
Yen, David W L ; Patel, Janak H. ; Davidson, Edward S.
Author_Institution :
IBM San Jose Research Laboratory
Abstract :
Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introduced. This steady-state model is most accurate overall. The queueing model is somewhat more accurate when request rate is near 1, and M and N are large. Accuracy is established with respect to probabilistic simulation. Additional related models are described.
Keywords :
Analytical models; memory bandwidth; memory interference; multiprocessor systems; performance evaluation; Communication networks; Computer networks; Delay; Interference; Multiprocessing systems; Multiprocessor interconnection networks; Network address translation; Process design; Switches; Very large scale integration; Analytical models; memory bandwidth; memory interference; multiprocessor systems; performance evaluation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1982.1675928
