Title :
Effects of Ti addition on via reliability in Cu dual damascene interconnects
Author :
Ueki, Makoto ; Hiroi, Masayuki ; Ikarashi, Nobuyuki ; Onodera, Takahiro ; Furutake, Naoya ; Inoue, Naoya ; Hayashi, Yoshihiro
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.
Keywords :
adhesion; copper; electromigration; grain growth; integrated circuit interconnections; reliability; semiconductor doping; voids (solid); Ta-Ti-TaN; Ti addition; Ti doping; adhesion improvement; adhesiveness improvements; copper interconnects; copper-titanium alloy; dual damascene interconnects; electrical performance; electrochemical-plated Cu film; grain growth; layer insertion; oxygen gettering effect; reliability improvements; stacked barrier metal; stress-induced voiding; tensile stress; via reliability; Copper; Doping; Electromigration; Gettering; Grain boundaries; Integrated circuit interconnections; Integrated circuit reliability; National electric code; Shape control; Stress; Copper interconnects; SIV; copper-titanium alloy; oxygen gettering; reliability; stress-induced voiding;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2004.837579