DocumentCode :
1146537
Title :
The Complexity of Fault Detection Problems for Combinational Logic Circuits
Author :
Fujiwara, Hideo ; Toida, Shunichi
Author_Institution :
Department of Electronic Engineering, Osaka University
Issue :
6
fYear :
1982
fDate :
6/1/1982 12:00:00 AM
Firstpage :
555
Lastpage :
560
Abstract :
In this correspondence we analyze the computational complexity of fault detection problems for combinational circuits and propose an approach to design for testability. Although major fault detection problems have been known to be in general NP-complete, they were proven for rather complex circuits. In this correspondence we show that these are still NP-complete even for monotone circuits, and thus for unate circuits. We show that for k-level (k ≥ 3) monotone/unate circuits these problems are still NP-complete, but that these are solvable in polynomial time for 2-level monotone/unate circuits. A class of circuits for which these fault detection problems are solvable in polynomial time is presented. Ripple-carry adders, decoder circuits, linear circuits, etc., belong to this class. A design approach is also presented in which an arbitrary given circuit is changed to such an easily testable circuit by inserting a few additional test-points.
Keywords :
Combinational circuits; computational complexity; design for testability; fault detection; polynomial algorithms; test generation; Adders; Circuit testing; Combinational circuits; Computational complexity; Decoding; Design for testability; Electrical fault detection; Linear circuits; Logic circuits; Polynomials; Combinational circuits; computational complexity; design for testability; fault detection; polynomial algorithms; test generation;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1982.1676041
Filename :
1676041
Link To Document :
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