DocumentCode
1146658
Title
Test Generation Algorithms for Computer Hardware Description Languages
Author
Levendel, Ytzhak H. ; Menon, Premachandran R.
Author_Institution
Bell Laboratories
Issue
7
fYear
1982
fDate
7/1/1982 12:00:00 AM
Firstpage
577
Lastpage
588
Abstract
This paper proposes an extension of the D-algorithm to functions described in computer hardware description languages. The proposed extension is applicable to both procedural and nonprocedural languages. Methods of D-propagation through the basic constructs of these languages and test generation for circuits containing functions described in CHDL´s are discussed. The fault modes considered are function variables stuck at 0 or 1, control faults, and function faults with user-specified faulty behaviors.
Keywords
D-algorithm; functional blocks; nonprocedural CHDL; procedural CHDL; test generation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Equations; Flip-flops; Hardware design languages; Registers; Sequential analysis; D-algorithm; functional blocks; nonprocedural CHDL; procedural CHDL; test generation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1982.1676054
Filename
1676054
Link To Document