Title :
Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
Author :
Sa, N. ; Kang, J.F. ; Yang, H. ; Liu, X.Y. ; He, Y.D. ; Han, R.Q. ; Ren, C. ; Yu, H.Y. ; Chan, D.S.H. ; Kwong, D.L.
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
In this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO2 gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called "turn-around" phenomenon, and the negative shifts of the threshold voltage (Vt) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characteristics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO2 and Si substrate and the diffusion/drift of oxygen ions (O-) from Si-O bonds into HfO2 layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (Ea) is consistent with the one predicted by the ESIDG mechanism.
Keywords :
CMOS integrated circuits; crystal defects; electron traps; hafnium compounds; insulated gate field effect transistors; reaction-diffusion systems; stress effects; tantalum compounds; 0.95 nm; Si-O bonds; TaN-HfN-HfO2; activation energy; electric stress-induced defect generation; electron-induced breaking; equivalent oxide thickness; gate stack; high-K gate dielectric; interfacial layer; oxygen ions; positive-bias temperature instability; preexisting traps; reaction-diffusion model; threshold voltage; turn-around phenomenon; CMOS technology; Character generation; Dielectric measurements; Hafnium oxide; Helium; Rapid thermal annealing; Semiconductor device modeling; Stress; Temperature; Threshold voltage; Electric stress-induced defect generation (ESIDG); high-; positive-bias temperature instability (PBTI); reaction–diffusion (R–D) model;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2005.853683
