Test counting: a tool for VLSI testing

The authors present a technique, called test counting, for analyzing the testing requirements imposed on a combinational network in the form of a set of stuck-at faults to be detected. By solving a large set of mathematical inequalities, called constraints, test counting determines that certain pairs of faults cannot be test simultaneously. The result is a set of mutually independence faults, no two of which can be detected by the same test vector. The number of faults becomes a lower bound on the size of the test set required. The authors provide a list of constraints to implement the test-counting algorithm and offer a complete minimal test set for the 74LS181 ALU.<>