Title :
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
Author :
Rosenberg, Arnold L.
Author_Institution :
Department of Computer Science, Duke University
Abstract :
This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array´s communication links rather than in its processing elements (PE´s). The major characteristics of the designs produced are as follows.
Keywords :
Arrays of processors; design for testability; dynamic fault tolerance; fault-tolerant design; grids of processors; linear arrays of processors; reconfigurable designs; trees of processors; Binary trees; Circuit faults; Circuit testing; Computer science; Fault tolerance; Integrated circuit interconnections; Process design; Redundancy; Switches; Wires; Arrays of processors; design for testability; dynamic fault tolerance; fault-tolerant design; grids of processors; linear arrays of processors; reconfigurable designs; trees of processors;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676134
