Title :
Redundancy and Don´t Cares in Logic Synthesis
Author_Institution :
IBM Thomas J. Watson Research Center
Abstract :
A signal in a logical network is called redundant if it can be replaced by a constant without changing the function of the network. Detecting redundancy is important for two reasons: guaranteeing coverage in stuck-fault testing, and simplifying multilevel logic without converting to two levels. In particular, removing redundancy allows simplification in the presence of don´t cares. The algorithm for redundancy removal described in this paper has been used successfully for both of the above purposes. It achieves savings in computer resources at the expense of possibly failing to discover some redundancies.
Keywords :
Don´t cares; logic synthesis; optimization; redundancy; testability; Helium; Intelligent networks; Logic design; Logic testing; Manufacturing; Minimization; Network synthesis; Programmable logic arrays; Redundancy; Signal synthesis; Don´t cares; logic synthesis; optimization; redundancy; testability;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676139
