Title :
Delayed-Staging Hierarchy Optimization
Author :
Silberman, Gabriel M.
Author_Institution :
IBM Thomas J. Watson Research Center
Abstract :
A geometric programming model is developed to optimize delayed-staging (DS) storage hierarchies. These hierarchies have direct paths between the CPU and the k fastest storage levels (k = 1 in a linear hierarchy), allowing for some concurrency in the flow of data through the hierarchy. The criterion for optimization is the minimization of average hierarchy access time subject to budgetary limitations, given the cache access time and the backing-store capacity.
Keywords :
Average access time; delayed-staging; geometric programming; miss ratios; storage hierarchies; Cache storage; Central Processing Unit; Computer science; Concurrent computing; Constraint optimization; Cost function; Delay effects; Linear programming; Parallel processing; Solid modeling; Average access time; delayed-staging; geometric programming; miss ratios; storage hierarchies;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676153
