Title :
Characterization of soft errors caused by single event upsets in CMOS processes
Author :
Karnik, T. ; Hazucha, P.
Author_Institution :
Circuit Res., Intel Labs, Hillsbow, OR, USA
Abstract :
Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.
Keywords :
CMOS integrated circuits; VLSI; alpha-particle effects; errors; fault tolerance; integrated circuit design; memory architecture; microprocessor chips; sequential circuits; CMOS processes; Si; VLSI circuits; accelerated measurement; charge collection effects; design parameter; error tolerance; high-intensity neutron beam; high-performance microprocessors; logic circuits; memory circuits; power-performance-area trade offs; radiation particle interactions; radiation-induced single event upsets; sequential logic cells; silicon; soft error characterization; soft error rate; system reliability; technology scaling trends; CMOS process; CMOS technology; Error analysis; Logic circuits; Microprocessors; Reliability; Silicon; Single event transient; Single event upset; Very large scale integration; 65; Index Terms- High performance; error tolerance; reliability; single event upset.; soft error;
Journal_Title :
Dependable and Secure Computing, IEEE Transactions on
DOI :
10.1109/TDSC.2004.14
