Baud-rate channel equalization in nanometer technologies

Chip design technology has been accelerating the advances of the communication technology in the past decades because a chip with larger computing capacity can support a communication system of higher transmission bandwidth. Since the communication transceivers are now in the multigiga bits/second range, the computing bandwidth requirement for a transceiver has grown into several hundreds of giga-FLOPs second range. To support such big computing tasks on a chip, nanometer technology and pure baud-rate computing without pipelining and oversampling overheads will be much more important. Meanwhile, baud-rate computing does not require extra-digital control for the digital-signal processing functions. This can greatly reduce the power consumption and chip area of a VLSI system. Yet, there are several design issues, such as the output signal-to-noise ratio, algorithmic mapping for computing model, and the critical path for the datapath design of the VLSI computing function, which need to be resolved under small silicon area requirements A novel baud-rate channel equalization architecture based on training coefficient relaxation techniques is presented in this paper to resolve these issues in nanotechnology such as 130- and 90-nm technologies. This design paradigm clearly demonstrates its advantage to enable multiport transceiver system-on-a-chip designs in nanometer technology. Trends for the baud-rate computing in smaller geometry are also explained.