Demonstration of a high performance 4H-SiC vertical junction field effect transistor without epitaxial regrowth

A high performance 4H-SiC vertical junction field effect transistor (VJFET) has been designed and fabricated using a self-aligned process which permits the formation of a highly vertical p⁺n junction gate and eliminates the need for epitaxial regrowth. Near 100% edge termination has been achieved, allowing the VJFETs to reach 392 V with a blocking layer of only 1.33 μm doped to 2 × 10¹⁶ cm^-3, reaching a record low R_{ON_SP} of 1.4 mΩ cm² at J_D up to 348 A/cm².