Title :
Statistical process modelling for 32nm high-K/metal gate PMOS device
Author :
Afifah Maheran, A.H. ; Noor Faizah, Z.A. ; Menon, P. Susthitha ; Ahmad, Ishtiaq ; Apte, Prakash R. ; Kalaivani, T. ; Salehuddin, F.
Author_Institution :
Inst. of Microeng. & Nanoelectron. (IMEN), Univ. Kebangsaan Malaysia (UKM), Bangi, Malaysia
Abstract :
The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore´s Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction.
Keywords :
MOSFET; Taguchi methods; hafnium compounds; high-k dielectric thin films; semiconductor device models; statistical analysis; titanium compounds; ATHENA; ATLAS; HfO2-TiSi2; ITRS prediction; MOSFET technology; Moore law; PMOS transistor; Taguchi L9 orthogonal method; VWF Silvaco TCAD tools; device scaling; high-k/metal gate PMOS device; leakage current; size 32 nm; statistical process modelling; threshold voltage optimization; virtual wafer fabrication; voltage 0.1030075 V; High K dielectric materials; Implants; Logic gates; MOSFET; Metals; Threshold voltage; 32nm PMOS; High-K dielectrics; Metal Gate Transistor; Silvaco; Taguchi Method;
Conference_Titel :
Semiconductor Electronics (ICSE), 2014 IEEE International Conference on
Conference_Location :
Kuala Lumpur
DOI :
10.1109/SMELEC.2014.6920839
