Field programmable gate arrays and floating point arithmetic

We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA´s permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA´s also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA´s for floating-point arithmetic.<>