Title :
On broad-side delay test
Author :
Savir, Jacob ; Patil, Srinivas
Author_Institution :
Technol. Products Div., IBM Corp., Hopewell Junction, NY, USA
Abstract :
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit\´s response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broadside delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy.<>
Keywords :
delays; integrated circuit testing; integrated logic circuits; logic testing; ISCAS sequential benchmarks; broad-side delay test; combinational circuit response; scan-based delay test; test vector generation; Benchmark testing; Circuit faults; Circuit testing; Clocks; Delay effects; Jacobian matrices; Logic circuits; Logic testing; Propagation delay; Sequential analysis;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
